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? semiconductor components industries, llc, 2014 april, 2014 ? rev. 11 1 publication order number: mc100lvep34/d mc100lvep34 2.5v / 3.3v?ecl 2, 4, 8 clock generation chip the mc100lvep34 is a low skew 2, 4, 8 clock generation chip designed explicitly for low skew clock generation applications. the internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. the v bb pin, an internally generated voltage supply, is available to this device only. for single?ended input conditions, th e unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. the common enable (en ) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the low state. this avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. an internal runt pulse could lead to losing synchronization between the internal divider stages. the internal enable flip?flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input. upon start?up, the internal flip?flops will attain a random state; the master reset (mr) input allows for the synchronization of the internal dividers, as well as multiple lvep34s in a system. single?ended clk input operation is limited to a v cc 3.0 v in pecl mode, or v ee ?3.0 v in necl mode. features ? 35 ps output?to?output skew ? synchronous enable/disable ? master reset for synchronization ? the 100 series contains temperature compensation. ? pecl mode operating range: v cc = 2.375 v to 3.8 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = ?2.375 v to ?3.8 v ? open input default state ? lvds input compatible ? these are pb?free devices so?16 d suffix case 751b 1 16 marking diagrams* a = assembly location l, wl = wafer lot y = year w, ww = work week g or = pb?free package 1 16 100lvep34g awlyww tssop?16 dt suffix case 948f *for additional marking information, refer to application note and8002/d. http://onsemi.com 1 16 100 vp34 alyw 1 16 see detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. ordering information (note: microdot may be in either location)
mc100lvep34 http://onsemi.com 2 v cc q0 q1 v cc q2 15 16 14 13 12 11 10 2 1 3 4 5 6 7 v cc 9 8 en nc clk clk v bb mr v ee d q r q r 2 q r 4 q r 8 warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. q0 q1 q2 figure 1. 16?lead pinout (top view) and logic diagram table 1. pin description pin function clk*, clk ** ecl diff clock inputs en* ecl sync enable mr* ecl master reset q0, q0 ecl diff 2 outputs q1, q1 ecl diff 4 outputs q2, q2 ecl diff 8 outputs v bb reference voltage output v cc positive supply v ee negative supply nc no connect * pins will default low when left open. **pins will default to v cc /2 when left open. table 2. function table clk en mr function z zz x l h x l l h divide hold q 0?3 reset q 0?3 z = low?to?high transition zz = high?to?low transition
mc100lvep34 http://onsemi.com 3 table 3. attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor 37.5 k esd protection human body model machine model charged device model > 2 kv > 200 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1) level 1 flammability rating oxygen index: 28 to 34 ul 94 v?o @ 0.125 in transistor count 210 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional moisture sensitivity information, refer to application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v ?6 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 ?6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma t a operating temperature range ?40 to +85 c t stg storage temperature range ?65 to +150 c ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm soic?16 soic?16 100 60 c/w c/w jc thermal resistance (junction?to?case) standard board soic?16 33 to 36 c/w ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm tssop?16 tssop?16 138 108 c/w c/w jc thermal resistance (junction?to?case) standard board tssop?16 33 to 36 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected.
mc100lvep34 http://onsemi.com 4 table 5. 100ep dc characteristics, pecl v cc = 2.5 v, v ee = 0 v (note 2) symbo l characteristic ?40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 40 50 60 40 50 60 42 52 62 ma v oh output high voltage (note 3) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv v ol output low voltage (note 3) 505 680 900 505 680 900 505 680 900 mv v ih input high voltage (single?ended) (note 4) 1335 1620 1335 1620 1275 1620 mv v il input low voltage (single?ended) (note 4) 505 900 505 900 505 900 mv v ihcmr input high voltage common mode range (differential) (note 4, note 5) 1.2 3.3 1.2 3.3 1.2 3.3 v i ih input high current 150 150 150 a i il input low current d d 0.5 ?150 0.5 ?150 0.5 ?150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. input and output parameters vary 1:1 with v cc . 3. all loading with 50 to v cc ? 2.0 v. 4. do not use v bb at v cc < 3.0 v. single?ended input clk pin operation is limited to v cc 3.0 v in pecl mode. 5. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc100lvep34 http://onsemi.com 5 table 6. 100ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 6) symbo l characteristic ?40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 40 50 60 40 50 60 42 52 62 ma v oh output high voltage (note 7) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 7) 1305 1570 1700 1305 1570 1700 1305 1570 1700 mv v ih input high voltage (single?ended) 2075 2420 2075 2420 2075 2420 mv v il input low voltage (single?ended) 1305 1700 1305 1700 1305 1700 mv v bb output voltage reference (note 8) 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v ihcmr input high voltage common mode range (differential) (note 9) 1.2 3.3 1.2 3.3 1.2 3.3 v i ih input high current 150 150 150 a i il input low current d d 0.5 ?150 0.5 ?150 0.5 ?150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. input and output parameters vary 1:1 with v cc . v ee can vary +0.925 v to ?0.5 v. 7. all loading with 50 to v cc ? 2.0 v. 8. single?ended input clk pin operation is limited to v cc 3.0 v in pecl mode. 9. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. table 7. 100ep dc characteristics, necl v cc = 0 v, v ee = ?3.8 v to ?2.375 v (note 10) symbo l characteristic ?40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 40 50 60 40 50 60 42 52 62 ma v oh output high voltage (note 11) ?1145 ?1020 ?895 ?1145 ?1020 ?895 ?1145 ?1020 ?895 mv v ol output low voltage (note 11) ?1995 ?1700 ?1600 ?1995 ?1700 ?1600 ?1995 ?1700 ?1600 mv v ih input high voltage (single?ended) ?1225 ?880 ?1225 ?880 ?1225 ?880 mv v il input low voltage (single?ended) ?1995 ?1600 ?1995 ?1600 ?1995 ?1600 mv v bb output voltage reference (note 12) ?1525 ?1425 ?1325 ?1525 ?1425 ?1325 ?1525 ?1425 ?1325 mv v ihcmr input high voltage common mode range (differential) (note 13) v ee +1.2 0.0 v ee +1.2 0.0 v ee +1.2 0.0 v i ih input high current 150 150 150 a i il input low current d d 0.5 ?150 0.5 ?150 0.5 ?150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. input and output parameters vary 1:1 with v cc . 11. all loading with 50 to v cc ? 2.0 v. 12. single?ended input clk pin operation is limited to v ee ?3.0 v in necl mode. 13. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc100lvep34 http://onsemi.com 6 table 8. ac characteristics v cc = 0 v; v ee = ?3.8 v to ?2.375 v or v cc = 2.375 v to 3.8 v; v ee = 0 v (note 14) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max f max maximum toggle frequency (see figure 4. f max ) 2.8 2.8 2.8 ghz t plh t phl propagation clk to q0, q1, q2 delay to output mr to q 550 500 650 600 750 700 600 550 700 650 800 750 650 600 750 700 850 800 ps t jitter rms clock jitter div2 2.5 ghz (see figure 4. f max /jitter) div2 3.0 ghz div4 2.5 ghz div4 3.0 ghz div8 2.5 ghz div8 3.0 ghz 0.36 0.34 0.26 0.32 0.27 0.32 0.4 0.4 0.4 0.30 0.40 0.29 0.38 0.30 0.39 0.4 0.5 0.5 0.35 0.63 0.33 0.60 0.34 1.10 0.6 0.5 0.5 ps t s setup time en 150 50 150 50 150 50 ps t h hold time en 200 100 200 100 200 100 ps t rr set/reset recovery 300 200 300 200 300 200 ps v pp input swing (note 15) 150 1000 150 1000 150 1000 mv t r t f output rise/fall times q (20% ? 80%) 90 170 200 100 180 250 120 200 280 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 to v cc ? 2.0 v. 15. v pp( min) is minimum input swing for which ac parameters guaranteed. the device has a dc gain of 40. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
mc100lvep34 http://onsemi.com 7 there are two distinct functional relationships between the master reset and clock: case 1: if the mr is de?asserted (h?l), while the clock is still high, the outputs will follow the second ensuing clock rising edge. clk q0 q1 q2 en the en signal will ?freeze? the internal divider flip?flops on the first falling edge of clk after its assertion. the interna l divider flip?flops will maintain their state during the freeze. when en is deasserted (low), and after the next falling edg e of clk, then the internal divider flip?flops will ?unfreeze? and continue to their next state count with proper phase rela - tionships. internal clock disabled internal clock enabled mr clk q0 q1 q2 en internal clock disabled internal clock enabled mr case 2: if the mr is de?asserted (h?l), after the clock has transitioned low, the outputs will follow the third ensuing clock rising edge. case 1 case 2 figure 2. timing diagrams clock output mr t rr clock output mr t rr figure 3. reset recovery time
mc100lvep34 http://onsemi.com 8 0 100 200 300 400 500 600 700 800 900 0 1000 2000 3000 4000 5000 6000 figure 4. f max frequency (mhz) 1 2 3 4 5 6 7 8 9 v outpp (mv) 4 / 8 2 figure 5. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v ordering information device package shipping ? MC100LVEP34DG soic?16 (pb?free) 48 units / rail mc100lvep34dr2g soic?16 (pb?free) 2500 / tape & reel mc100lvep34dtg tssop?16* 96 units / rail mc100lvep34dtr2g tssop?16* 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb?free.
mc100lvep34 http://onsemi.com 9 resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1672/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
mc100lvep34 http://onsemi.com 10 package dimensions tssop?16 case 948f?01 issue b ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. section n?n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ?t? ?v? ?w? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc100lvep34 http://onsemi.com 11 package dimensions soic?16 case 751b?05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 8x *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc100lvep34/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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